Flanger — HLE + bytecode
Flanger — HLE reconstruction and DSP bytecode
DSPHLE selector 0x04 · program image prog04_flanger · Intervention-pinned (a panel control was driven and the moving C-RAM cell identified).
swept delay + feedback; rate=0x05, feedback=0x00, depth=0x08.
This page pairs the bytecode the effect runs on the NEC µPD6383GF with the high-level reconstruction that makes it audible in MAME. The reconstruction is not the chip’s microcode — it is a textbook DSP block built from the decoded meaning of that microcode, and reading the two together is how the bytecode is understood (and, in time, driven toward a faithful low-level emulation). See also the signal-flow flowchart.
The bytecode below is the source of truth; the HLE reconstruction is not. The HLE is our best current interpretation and may contain mistakes — where the two disagree, the bytecode wins, and a better HLE should be updated here. This page is the permanent archive of the reference HLE: it is kept here even after the code is eventually removed from the MAME sources.
DSP bytecode (reverse-engineered microprogram)
The disassembled image the chip executes for this effect. Source (regenerable):
dsp/disasm/prog04_flanger.dsm.
; Reverse-engineered disassembly of the KN5000 effects-DSP microcode
; (NEC uPD6383GF), recovered from the original firmware. The microcode is the
; work of its original authors; this is a disassembly for preservation and
; interoperability, and no claim of copyright is made over the disassembled program.
; KN5000 effects-DSP program -- FLANGER
; image rep algo 4 | slots 4 | unit 0 (I-RAM load 84)
; family modulation | confidence medium | 65 words, 18 class-A multiplies (12 named)
; role: flanger: swept all-pass chain, 0.3 feedback, wet mix
; coefficient cursor base 0x00
;
; GENERATED by dsp/tools/gen_dsp_disasm.py -- DO NOT EDIT.
; Put labels/comments in the matching dsp/sym/*.sym; analysis in dsp/algorithms/.
w0 088013000B ?word 0x088013000B ; 880.1.30.00B hi12{ESC ?7 res=080} [external delay-DRAM READ (FORCED, adjudication-round5 sect. 3 -- addr8 bit 6 is the direction field and 0x60 is the WRITE; this REVERSES R1 F1, which bounded the read latency to one repetition when the descriptors need twenty words); this end moves with the user's DELAY (ms) knob, and the delay is READ_CELL - WRITE_CELL; addr8 0x30 also marks the FIRST DRAM access of a body, 37 of 38 distinct images (R3 sect. 6.2). external delay-DRAM access; address = DESCRIPTOR_CELL[k] + G, from the host bank behind pointer ...825 / tag 0x4C (R3, PROVEN BY CONSTRUCTION) -- the k-th class-1 escape word of a body takes the k-th cell of that body's own descriptor block (the IDENTITY map, FORCED in adjudication-round5 sect. 1), so the address is NOT in this word]
w1 00400008BC ?word 0x00400008BC ; 040.0.00.8BC hi12{?6 res=040} [SPECULATIVE: lo12 bit-11 modifier word + pointer-mode (bit11-family); the base selector/register is OPEN]
w2 00002051CD ld (p),(p)+5
w3 000020040E ld acc,(p)+0
w4 0212A011D5 mac (p),c+,(p)+1 ; mem[p]<-acc, acc=0
; C-RAM[0x00] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x00] = filter section cell 0 (role filter, INFERRED)
w5 0202A451D5 mac (p),c+,(p)+69
; C-RAM[0x01] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x01] = filter section cell 1 (role filter, INFERRED)
w6 0202AC01D5 mac (p),c+,(p)-64
; C-RAM[0x02] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x02] = filter section cell 2 (role filter, INFERRED)
w7 09001602D9 dly.w dsc[k],p+96
w8 0192AFB1D5 mac (p),c+,(p)-5 ; store SUPPRESSED (bit7)
; C-RAM[0x03] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x03] = filter section cell 3 (role filter, INFERRED)
w9 0182245000 mac.b (p)0,(p)+69
w10 000020044C ?word 0x000020044C ; 000.2.00.44C hi12{-} [SPECULATIVE (prospective, not measured): SRC 0x11 = ACCB (2nd accumulator); ACT 0x0C = delay READ]
w11 088012040B ?word 0x088012040B ; 880.1.20.40B hi12{ESC ?7 res=080} [external delay-DRAM READ (FORCED, adjudication-round5 sect. 3 -- addr8 bit 6 is the direction field and 0x60 is the WRITE; this REVERSES R1 F1, which bounded the read latency to one repetition when the descriptors need twenty words); this end moves with the user's DELAY (ms) knob, and the delay is READ_CELL - WRITE_CELL. external delay-DRAM access; address = DESCRIPTOR_CELL[k] + G, from the host bank behind pointer ...825 / tag 0x4C (R3, PROVEN BY CONSTRUCTION) -- the k-th class-1 escape word of a body takes the k-th cell of that body's own descriptor block (the IDENTITY map, FORCED in adjudication-round5 sect. 1), so the address is NOT in this word]
w12 0012201655 mac ta,(p)+1 ; mem[p]<-acc, acc=0
w13 01042001D5 post (p),(p)+0
w14 0A00000041 ?word 0x0A00000041 ; A00.0.00.041 hi12{ESC f98=2} [head of a fixed 3-word template (S-5); operands SRC 0x01/ACT 0x01 dark]
w15 08801202C7 dly.r dsc[k],p+32
w16 0102AB94C8 ?word 0x0102AB94C8 ; 102.A.B9.4C8 hi12{f98=1 f31=1} cur+ [gain multiply (same op in phaser all-pass and reverb diffuser)]
; C-RAM[0x04] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x04] = filter section cell 4 (role filter, INFERRED)
w17 0000204407 ld.st acc,(p)+4
w18 00002FA407 ld.st acc,(p)-6
w19 0092A00200 mac.b c,c+,(p)+0 ; store SUPPRESSED (bit7)
; C-RAM[0x05] (coeff, base 0x00 MEASURED)
w20 00822001C0 mac.b (p),(p)+0
w21 0094A00200 wrap acc,c+ ; acc <- datum(acc) & coef (LFO modulus)
; C-RAM[0x06] (coeff, base 0x00 MEASURED)
w22 0000200447 ?word 0x0000200447 ; 000.2.00.447 hi12{-} [SPECULATIVE (prospective, not measured): SRC 0x11 = ACCB (2nd accumulator)]
w23 0092200700 ?word 0x0092200700 ; 092.2.00.700 hi12{ST f31=1 ?7 res=080} [SPECULATIVE (prospective, not measured): SRC 0x1C = control/mod source into MAC (100% MAC-consumed; LFO in mod fx, envelope/AGC in dynamics) -- NOT LFO-only: present in 19 non-LFO programs (dsp_datapath_fingerprint)]
w24 0000A001D5 ld (p),c+,(p)+0
; C-RAM[0x07] (coeff, base 0x00 MEASURED)
w25 0182200000 mac.b (p)0,(p)+0
w26 0040000C63 ?word 0x0040000C63 ; 040.0.00.C63 hi12{?6 res=040} [SPECULATIVE (prospective, not measured): SRC 0x11 = ACCB (2nd accumulator)]
w27 00006184CD ?word 0x00006184CD ; 000.6.18.4CD hi12{-} [table-lookup idiom, class-6 addr8 = table selector (INFERRED)]
w28 00124011CE ?word 0x00124011CE ; 012.4.01.1CE hi12{ST f31=1} [table-lookup idiom, third word (INFERRED)]
w29 01042081CE post (p),(p)+8
w30 0102200000 mac.b (p)0,(p)+0
w31 0000A00415 ld acc,c+,(p)+0
; C-RAM[0x08] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x08] = op0x66[0] (role mix/tap, INFERRED)
w32 0212200000 mac.b (p)0,(p)+0 ; mem[p]<-acc, acc=0
w33 00002F9407 ld.st acc,(p)-7
w34 0092A00200 mac.b c,c+,(p)+0 ; store SUPPRESSED (bit7)
; C-RAM[0x09] (coeff, base 0x00 MEASURED)
w35 00822001C0 mac.b (p),(p)+0
w36 0094A00200 wrap acc,c+ ; acc <- datum(acc) & coef (LFO modulus)
; C-RAM[0x0A] (coeff, base 0x00 MEASURED)
w37 0000200447 ?word 0x0000200447 ; 000.2.00.447 hi12{-} [SPECULATIVE (prospective, not measured): SRC 0x11 = ACCB (2nd accumulator)]
w38 0092200700 ?word 0x0092200700 ; 092.2.00.700 hi12{ST f31=1 ?7 res=080} [SPECULATIVE (prospective, not measured): SRC 0x1C = control/mod source into MAC (100% MAC-consumed; LFO in mod fx, envelope/AGC in dynamics) -- NOT LFO-only: present in 19 non-LFO programs (dsp_datapath_fingerprint)]
w39 0000A001D5 ld (p),c+,(p)+0
; C-RAM[0x0B] (coeff, base 0x00 MEASURED)
w40 0182200000 mac.b (p)0,(p)+0
w41 0040000C63 ?word 0x0040000C63 ; 040.0.00.C63 hi12{?6 res=040} [SPECULATIVE (prospective, not measured): SRC 0x11 = ACCB (2nd accumulator)]
w42 00006184CD ?word 0x00006184CD ; 000.6.18.4CD hi12{-} [table-lookup idiom, class-6 addr8 = table selector (INFERRED)]
w43 00124011CE ?word 0x00124011CE ; 012.4.01.1CE hi12{ST f31=1} [table-lookup idiom, third word (INFERRED)]
w44 01042FE1CE post (p),(p)-2
w45 0102200000 mac.b (p)0,(p)+0
w46 0000AFE415 ld acc,c+,(p)-2
; C-RAM[0x0C] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x0C] = op0x66[1] (role mix/tap, INFERRED)
w47 021220A1CD mac (p),(p)+10 ; mem[p]<-acc, acc=0
w48 00002F81CE ld (p),(p)-8
w49 0212204407 mac.st acc,(p)+4 ; mem[p]<-acc, acc=0
w50 0000AFF1D5 ld (p),c+,(p)-1
; C-RAM[0x0D] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x0D] = filter section cell 0 (role filter, INFERRED)
w51 0202A481D5 mac (p),c+,(p)+72
; C-RAM[0x0E] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x0E] = filter section cell 1 (role filter, INFERRED)
w52 0202AB51D5 mac (p),c+,(p)-75
; C-RAM[0x0F] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x0F] = filter section cell 2 (role filter, INFERRED)
w53 09001602D9 dly.w dsc[k],p+96
w54 0192A031D5 mac (p),c+,(p)+3 ; store SUPPRESSED (bit7)
; C-RAM[0x10] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x10] = filter section cell 3 (role filter, INFERRED)
w55 0182248000 mac.b (p)0,(p)+72
w56 000020044C ?word 0x000020044C ; 000.2.00.44C hi12{-} [SPECULATIVE (prospective, not measured): SRC 0x11 = ACCB (2nd accumulator); ACT 0x0C = delay READ]
w57 088012040B ?word 0x088012040B ; 880.1.20.40B hi12{ESC ?7 res=080} [external delay-DRAM READ (FORCED, adjudication-round5 sect. 3 -- addr8 bit 6 is the direction field and 0x60 is the WRITE; this REVERSES R1 F1, which bounded the read latency to one repetition when the descriptors need twenty words); this end moves with the user's DELAY (ms) knob, and the delay is READ_CELL - WRITE_CELL. external delay-DRAM access; address = DESCRIPTOR_CELL[k] + G, from the host bank behind pointer ...825 / tag 0x4C (R3, PROVEN BY CONSTRUCTION) -- the k-th class-1 escape word of a body takes the k-th cell of that body's own descriptor block (the IDENTITY map, FORCED in adjudication-round5 sect. 1), so the address is NOT in this word]
w58 0012201655 mac ta,(p)+1 ; mem[p]<-acc, acc=0
w59 01042001D5 post (p),(p)+0
w60 0A00000041 ?word 0x0A00000041 ; A00.0.00.041 hi12{ESC f98=2} [head of a fixed 3-word template (S-5); operands SRC 0x01/ACT 0x01 dark]
w61 08801202C7 dly.r dsc[k],p+32
w62 0102AB84C8 ?word 0x0102AB84C8 ; 102.A.B8.4C8 hi12{f98=1 f31=1} cur+ [gain multiply (same op in phaser all-pass and reverb diffuser)]
; C-RAM[0x11] (coeff, base 0x00 MEASURED)
; coeff C-RAM[0x11] = filter section cell 4 (role filter, INFERRED)
w63 0880160000 dly.w dsc[k],p+96
w64 040010E407 endblk #0E ; END OF BLOCK -- the last word of a block
HLE reconstruction (MAME, kn5000_tonegen.cpp)
The decode of the bytecode above, rebuilt as audible DSP. Two parts: the parameter refresh
(reads the decoded C-RAM coefficient cells once per update) and the per-sample insert (the
signal processing). Default OFF, behind the DSPHLE research port. Source:
src/mame/matsushita/kn5000_tonegen.cpp.
Parameter refresh (decode the C-RAM coefficients):
const bool fl_hle = (dsphle == 4);
double fl_inc = 0.0, fl_depth = 0.0, fl_base = 0.0, fl_fb = 0.0;
if (fl_hle)
{
auto q22f = [](u32 v) -> double {
int32_t s = (v & 0x800000) ? int32_t(v) - 0x1000000 : int32_t(v);
return double(s) / 4194304.0; };
const bool bit1 = (dspcfg & 2) != 0;
const double cs = bit1 ? 1.0 : 2.0; // operand -> cell scale
const double inc = double(m_dsp1->cram_read(0x05) & 0xffffff) * cs; // phase incr (cell scale)
const double f_hz = inc * 44100.0 / 8388608.0;
fl_inc = std::clamp(f_hz, 0.02, 12.0) / double(STREAM_RATE);
// DEPTH cell (0..1) scales a max LFO sweep of ~5 ms (240 samples @44.1k), -> stream rate
const double depth01 = std::clamp(q22f(m_dsp1->cram_read(0x08)) * cs, 0.0, 1.0);
fl_depth = depth01 * 240.0 * double(STREAM_RATE) / 44100.0;
fl_base = 2.0; // very short base (high notches)
fl_fb = std::clamp(q22f(m_dsp1->cram_read(0x00)) * cs * 0.5, -0.95, 0.95); // feedback = operand
}
Per-sample insert (the reconstructed signal path):
if (fl_hle)
{
m_fl_phase += fl_inc;
if (m_fl_phase >= 1.0) m_fl_phase -= 1.0;
const double d = fl_base + fl_depth * (0.5 + 0.5 * std::sin(2.0 * M_PI * m_fl_phase));
const double sl = double(mix_l) / 32768.0, sr = double(mix_r) / 32768.0;
const double tl = m_fl_l.read(d), tr = m_fl_r.read(d);
m_fl_l.write(sl + fl_fb * tl);
m_fl_r.write(sr + fl_fb * tr);
mix_l = int32_t((0.5 * sl + 0.5 * tl) * 32768.0);
mix_r = int32_t((0.5 * sr + 0.5 * tr) * 32768.0);
}